1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) fabrication, and more particularly, to a method of forming a trench capacitor for a dynamic random access memory cell.
2. Description of the Prior Art
The increasing popularity of electronic equipment such as computers has driven the demand for large semiconductor memories. The array configuration of semiconductor memory lends itself well to the regular structure preferred in "very large scale integration" (VLSI) integrated circuits. Dynamic random access memories (DRAMs) have become one of the most widely used types of semiconductor memory due to its low cost per bit, high device density and flexibility of use concerning reading and writing operations.
Early DRAMs used storage cells each consisting of three transistors and were manufactured using P type channel metal-oxide-semiconductor (PMOS) technology. Later, a DRAM storage cell structure consisting of one transistor and one capacitor was developed. The gate of the transistor is controlled by a word line signal, and data, represented by the logic level of a capacitor voltage, is written into or read out of the capacitor through a bit line.
As the semiconductor memory device becomes more highly integrated, the area occupied by a capacitor of a DRAM storage cell typically shrinks. Thus, the capacitance of the capacitor is reduced owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, thereby achieving both high cell integration and reliable operation.
When DRAM cells are scaled down while maintaining cell capacitance, three-dimensional cell structures, such as trench capacitors, are widely developed. One of advantages of the trench capacitor cell is its large capacitance and planar topography. However, trench-to-trench leakage current becomes a primary constraint, especially when the trench-to-trench spacing in the DRAMs is reduced below 0.8 .mu.m. This trench-to-trench leakage problem is widely discussed in, for example, the reference by B. W. Shen et al., "Scalability of a Trench Capacitor Cell for 64 Mbit DRAM," IEDN Tech. Dig., 1989, pages 27-30, and the reference by Takeshi Hamamoto et al., "Characterization of the Cell Leakage of a Stacked trench Capacitor (STT) Cell," IEEE Transactions on Electron Devices, Vol. 41, No. 10, October, 1994, pages 1801-1805, which are hereby incorporated by reference.